1. Field of the Invention
The present invention relates to a crosstalk verification device for automatically verifying the presence/absence of a portion in which there is a danger that crosstalk may occur for a layout pattern of a designed LSI.
2. Description of the Background Art
In an integrated circuit, a transistor of low output impedance has a large driving capability. The output waveform on an output wire of the transistor exhibits steep grades and consequently contains large high-frequency components. Thus the transistor of low output impedance is prone to exert the influence of crosstalk on other wires. On the other hand, a transistor of high output impedance is less capable of cancelling noise, if generated on an output wire thereof, because of its small driving capability. Thus the transistor of high output impedance is susceptible to crosstalk from other wires. Conventionally, a designer has visually confirmed the presence/absence of a portion in which there is a danger that the crosstalk may occur for a layout pattern of a designed LSI. The designer, while visually pursuing the layout pattern, has identified in the pattern the transistor of low output impedance which is prone to exert crosstalk influence and the transistor of high output impedance which is susceptible to crosstalk and has followed the output wires of the transistors to infer the combination and places of the output wires which are prone to cause the crosstalk.
However, the visual verification by the designer has the drawback of a seriously heavy burden on the designer. Another drawback is that the portion having the crosstalk occurrence danger is often overlooked because of its visual inference.
In view of scale expansion of the integrated circuits and size reduction of the patterns in future, the visual verification by the designer is expected to become more difficult to achieve correct crosstalk verification.